Every folder under examples/ is a pcbjs project: clone the repository, build it, and run pcbjs check in one. The demo boards are the small ones the documentation refers to. The review boards were each built by a reviewer from an empty folder to an orderable board, and are larger: USB hubs, an Ethernet PHY, an SDRAM, a buck converter, a stack of three boards.
The numbers on each card come from pcbjs check --json at the time the site was built: parts, pads, tracks, vias, nets, the legs the autorouter laid, the DRC and ERC counts and the compile time. The pictures are pcbjs shot of the same build, 3D and 2D.
the four demo boards: Blinky, three LED channels split over schematic, sourcing and layout files; Coin, the smallest board; Quad, four layers; Multi, one design for three fab targets with variants
Known findings: none, and they must stay clean
blinky.pcb.tsxBlinky: three LED channels switched by one transistor on a 30 x 20 mm two-layer board, in three files: blinky.sch.tsx has the nets, parts and schematic picture, blinky.sourcing.ts the part numbers, and this file the layout.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 734 ms
coin.pcb.tsxCoin: two test pads on the battery net of a 20 mm round board.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 77 ms
quad.pcb.tsxQuad: a divider on a 30 x 15 mm four-layer board, with SIG on In1.Cu between a via pair and a ground plane on In2.Cu.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 88 ms
multi.pcb.tsxMulti: the Coin idea built for three fabs at once, JLCPCB 2-Layer, OSH Park 2-Layer and a house target with a 0.2 mm clearance and a black mask.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 47 ms
a USB-C to header adapter with 90 ohm differential pairs, a via pair, ESD array and a length matched four line bus on four layers
pcb.tsxhighspeed: a USB-C to 4-pin USB 2.0 header adapter with an ESD array, and a four line data bus between two headers whose lines are length matched, 44 x 24 mm, four layers: signals on F.Cu and B.Cu, GND on In1.Cu, VBUS on In2.Cu.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 1.0 s
a round OSH Park badge: charlieplexed rim LEDs, curved text, silk logo, a lanyard slot, a pogo programming array and a coin cell on the back
pcb.tsxBadge: a round 40 mm wearable badge with a flat bottom edge, an ATtiny85 charlieplexing six rim LEDs, run from a CR2032 on the back.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 2.3 s
an ESP32-C3 sensor node, 40 by 30 mm on two layers, built from the README and docs alone
pcb.tsxESP32 sensor node: ESP32-C3-MINI-1, USB-C with ESD, 3.3 V LDO, BME280, reset and boot buttons, status LED and debug header on a 40 x 30 mm two-layer board.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 4.8 s
a gigabit PHY module, QFN48, magjack and two RGMII match groups of six lines tuned to 0.12 mm, four layers
Known findings: one silk-over-edge warning: the RJ45 overhangs the board edge by design
pcb.tsxeth-phy: a gigabit Ethernet PHY module.
DRC 0 errors, 1 warning · ERC 0 errors, 0 warnings · compiled in 6.0 s
an N by N WS2812B-2020 matrix built from a circuit placed per pixel, serpentine data chain, pours on both sides
pcb.tsxLED matrix: N x N WS2812B-2020 pixels on a two-layer board, chained in a serpentine from J1 at the top to J2 at the bottom.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 3.0 s
five 100 ohm LVDS pairs with array ends, an I2C level shifter and two custom footprints on four layers
pcb.tsxlvds-camera: a camera link adapter, 60 x 18 mm, JLCPCB four layer.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 2.6 s
three boards in one folder, controller, driver and test jig, sharing lib/; the driver lays out a half bridge circuit three times
Known findings: driver keeps the ERC warning copper-weight: 2 oz copper under the 1 oz preset rules, kept because the 0.16 mm rules reroute it into split pours
pcb.tsxController: STM32G431 with FDCAN, 60 x 45 mm, two layers.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 26.8 s
three boards in one folder, controller, driver and test jig, sharing lib/; the driver lays out a half bridge circuit three times
Known findings: driver keeps the ERC warning copper-weight: 2 oz copper under the 1 oz preset rules, kept because the 0.16 mm rules reroute it into split pours
pcb.tsxDriver: IR2133S three phase gate driver and six DPAK MOSFETs, 60 x 62 mm, two layers of 2 oz copper.
DRC 0 errors, 0 warnings · ERC 0 errors, 1 warning · compiled in 4.8 s
three boards in one folder, controller, driver and test jig, sharing lib/; the driver lays out a half bridge circuit three times
Known findings: driver keeps the ERC warning copper-weight: 2 oz copper under the 1 oz preset rules, kept because the 0.16 mm rules reroute it into split pours
pcb.tsxJig: a 60 x 45 mm bed of nails for the controller.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 9.3 s
a 24 V to 5 V 5 A buck, copper first: power pours, thermal maps, arcs in the outline and a cutout, 2 oz copper, vendor STEP models
Known findings: none: the regulator's SW, PGND and VIN bars take a 0.02 mm mask margin, inside TI's 0.05 maximum, to keep the 0.13 mm dam black mask needs
pcb.tsxPSU: 24 V in, 5 V 5 A out, a TPS56637 synchronous buck on a 64 x 42 mm 2-layer board with 2 oz copper.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 1.6 s
a QFN64 broken out to four headers by 76 autorouted legs; tangled.tsx turns every header end for end and routes with manual stubs and vias
pcb.tsxQFN breakout: a QFN64 at 0.5 mm pitch broken out to four 16 pin headers in pin order, every pin a bare route(a, b).
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 5.5 s
an STM32F429 with a 16-bit SDRAM on four layers: 91 autorouted legs and two match groups on a timing budget
Known findings: one length-match error on DATA: the FMC data pins sit on the far sides of the MCU and the only free board lies behind ADDR, so closing it needs the SDRAM moved or the inner layers opened
pcb.tsxsdram: an STM32F429ZI with a 16-bit SDRAM on its FMC, 55 x 45 mm, four layers on the JLCPCB preset: signals on F.Cu and B.Cu, GND on In1.Cu, 3V3 on In2.Cu.
DRC 1 error, 0 warnings · ERC 0 errors, 0 warnings · compiled in 28.9 s
a Raspberry Pi HAT in the official outline with 11 model files from KiCad and LCSC
Known findings: none: the 0.5 mm pitch accelerometer has one gang mask opening per pad row
pcb.tsxSensor HAT: a Raspberry Pi HAT with BME280, LIS3DH, an OLED header, micro SD, a LiPo charger on USB-C, the HAT ID EEPROM, a buzzer, two buttons and a WS2812B-2020.
DRC 0 errors, 0 warnings · ERC 0 errors, 4 warnings · compiled in 12.2 s
an STM32F103 board for JLCPCB and OSH Park four layers from one design
pcb.tsxstm32-dev: an STM32F103C8 dev board, 50 x 35 mm, four layers: signals on F.Cu and B.Cu, GND on In1.Cu, 3V3 on In2.Cu.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 3.9 s
a four port USB 2.0 hub on two layers, every pair from an impedance class with array ends
pcb.tsxusb-hub: a bus powered four port USB 2.0 hub, 50 x 30 mm, JLCPCB two layer.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 8.6 s
a four port USB 3.2 hub on the 3313 four layer preset: SuperSpeed pairs through AC capacitors and ESD arrays, match groups per port, 115 autorouted legs
pcb.tsxusb3-hub: a bus powered four port USB 3.2 Gen 1 hub, 72 x 44 mm, JLCPCB four layer 3313 stackup.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 19.6 s
the smallest review board: a 5 V USB-C sink, an LDO, two LEDs and a header
Known findings: none: the USB-C receptacle's GND and VBUS pads, 0.15 mm apart, share a gang mask opening at each end
pcb.tsxusbc-led: USB-C 5 V in, AP2112K 3.3 V LDO, power LEDs on 5 V and 3.3 V, a 4-pin header breaking out 3.3 V and GND.
DRC 0 errors, 0 warnings · ERC 0 errors, 0 warnings · compiled in 1.0 s